MindTree’s approach to Bluetooth Baseband design provides maximum flexibility to chip vendors without compromising performance parameters such as processor load and memory requirements. Compliant with Bluetooth 1.1 specifications, the Ethermind Baseband Controller is available as silicon proven synthesizable Verilog core with LMP / HCI firmware. The IP can be reconfigured to work with any 8 / 16 / 32 bit microcontroller on which LMP / HCI firmware resides and be reconfigured to interface with many Bluetooth radio implementations.

Voice applications can easily be built, as the SCL data transfer is supported in the Ethermind Baseband design itself. The core executes all datapath functions with error detection and correction logic in addition to the management and control of the lower layer protocol. The Ethermind Baseband core also manages channel selection and hopping functions, relieving the host processor(s) to manage only the LMP / HCI layer functions. Intelligent radio control ensures low power consumption in addition to alternately low power features of Bluetooth wireless technology.

EtherMind Baseband architecture is flexible enough to support various on-chip FIFOs and sizes to enable optimal custom application designs. With minimum processor load and chip power consumption, fabless companies can easily customize EtherMind Baseband to develop the lowest foot print SOC design for any target application.