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Forward Error Correction (FEC) is one of the key parts of any digital communication system (especially systems that send the information in a noisy error-prone environment) for lowering the signal power required for the reliable data transfer. It computes and adds the redundant information to the data while transmitting. The receiver uses this redundant information to correct the errors. Convolution encoder along with Viterbi decoder is an excellent FEC technique for correcting random errors. It is one of the most widely used FEC method in many digital communication systems - Cellular, Video/audio broadcast, WLAN, Satellite communications etc.
 

MindTree offers a highly generic and parameterizable Convolution encoder and Viterbi decoder core to meet the needs of any FEC application. This is the industry’s first FEC IP providing a generic solution addressing all the features.
Convolution encoder >
Viterbi decoder >
Salient Features:
Synthesizable core
Completely generic and Parameterizable
 
Encoder rate with/without puncturing
Trace back depth
Constraint length
Encoder Polynomials
Puncture patterns
Hard/soft inputs
Soft input width
Continuous/block decoding
Representation of soft inputs - 2's complement/offset binary/sign-magnitude
Optional Input phase/node synchronization
Optional Auto/external synchronization
Optional BER monitor
Optional Differential Encoder/decoder
Built-in path metric normalization
Option for an external Survivor memory (Trace-back memory)
Multiple styles of implementation - Serial, Parallel and hybrid architectures to meet speed/area requirements
Available for both ASIC and FPGA platforms
Available in both Verilog and VHDL
Customization is available for any specific requirement/application.
Typical Applications
3G cellular - CDMA2000, W-CDMA, TD-SCDMA
DVB, DAB
LMDS, MMDS
WLAN-802.11a
xDSL
Cable modem
Satellite communications
Deliverables
Design document
RTL source code
C model test setup(for AWGN channel)
Test-bench and scripts to run the tests
User manual/guide - parameterization instructions
FPGA specific Netlist/PAR database (for FPGA solution)
ASIC specific netlist/scripts (for ASIC solution)