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MindTree’s approach to WLAN MAC design provides maximum flexibility
to chip vendors without compromising performance parameters
such as processor load and memory requirements. Compliant
with both IEEE 802.11 a and b specifications, the WLAN MAC
core is available as silicon proven synthesizable Verilog
core with protocol software. The IP can be reconfigured to
work with any 8/16/32 bit microcontroller on which protocols
reside and be reconfigured to interface with both a and b
WLAN Baseband implementations. The WLAN MAC core also conforms
with IEEE 802.11e specifications.
Customers can quickly develop IEEE compliant 802.11 MAC chips
or integrate the MAC functionality into SOC designs.
The MAC architecture is flexible enough to support various
on-chip FIFOs and sizes to enable optimal custom application
designs. With minimum processor load and and chip power consumption,
fabless companies can easily customize MAC IP to develop the
lowest foot print SOC design for both access point and station
applications.
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| Features |
| The WLAN Media Access Controller
(MAC) supports the following features: |
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Supports
IEEE 802.11 a, b Access Point and Station Features |
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Complies
with IEEE 802.11e specifications for QoS implementation |
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Supports
optional FEC for data integrity |
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Technology
independent synthesizable Verilog core |
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Supports
Infrastructure / Independent BSS |
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Supports
Data rates up to 54 Mbps |
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Re-configurable
processor host interface (default ARM interface) |
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Interface
to DSSS Radio Chip Set |
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Re-configurable
FIFO size |
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Supports
Distributed Coordination Function (DCF) |
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Supports
Point Coordination Function (PCF) |
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Baseband
and Frequency Synthesizer Configuration |
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ACK / CTS
Management |
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Beacon Frame
Monitoring |
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Host Command
Processing |
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Incoming
Traffic Processing |
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Power Management
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WEP Support
(64bit and 128bit key) |
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| Deliverables |
| The package consists of the following
components: |
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RTL synthesizable
Verilog core |
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Synthesis
scripts |
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Test environment
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Golden test
cases |
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Design and
verification documents |
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Application
documents |
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User manual
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| Applications |
| This finds applications in Infrastructure
BSS Networks, Independent Basic Service Set (IBSS) Networks. |
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| Micro Controller |
| Interacts with the microcontroller
allowing READ and WRITE transactions from / to the microcontroller
and MAC controller internal blocks. |
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| Command Decoder |
| Decodes the commands given by host
and accordingly enables the internal blocks - Receiver Block,
DCF State Machine to trigger the Transmitter Block. The Command
Decoder triggers Baseband controller configuration and channel
configuration (Freq Synthesizer Configuration). It further determines
when the Beacon Time Interval occurs and accordingly gives an
early TBTT (Target Beacon Transmission Time) indication. The
Local Timer Counter, which is 64 bits counter, is loaded with
Time Stamp of the received Frame. The Beacon Timer ensures that
at every Beacon Interval there is a Beacon Frame Reception. |
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| MAC FIFO Manager |
| Manages read / write operations to
or from on chip FIFOs with the status updation logic. There
are two FIFO’s in the MAC Controller – the first FIFO for the
Receive operation, during which the Receiver Block dumps the
received Frame into it and where the micro controller reads
the received frames from this FIFO. The second FIFO is meant
for Transmit operation during which the microcontroller puts
the frame from its application and is transmitted. |
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| Transmitter |
| Deals with the transmission of MAC
Frames. It transmits only when it is triggered by DCF Block
and interacts with the Transmit port of the Phy chip. Data transmission
occurs serially. The Transmitter enables its station to retry
the transmission after it has determined the occurrence of Time
Out for that frame sent. Generates the Interrupts like ACK /
CTS / Retry Over / Time Out Interrupts. Manages retransmissions
based on the ACK status of the received frames. |
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| Framer |
| Responsible for Frame Header Framing.
It closely interacts with the Transmitter Block and the Register
Block. On getting triggered by the Transmitter Block, it reads
appropriate registers of the Register Block and forwards the
MAC Header information to Transmitter. |
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| DCF |
| Implements the Virtual carrier sense
mechanism thereby leading to collision avoidance. It determines
whether the medium is Idle or not and hence accordingly initiates
Transmission of Host Frames. It implements Back-Off procedure. |
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| Interrupt Block |
| Drives the Interrupt line if any
of the sources of Interrupt is active. It withdraws the Interrupt
once all the sources of interrupt are cleared. Sources of Interrupt
can be masked through Interrupt Mask Register. |
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| Register Block |
| Comprises of the Registers required
for MAC operation. Host programs use these Registers with suitable
parameters whenever it wants to transmit a frame. There is a
status register, which indicates the status of MAC. |
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| Receiver |
| Deals with the reception of MAC Frames
and interacts with the Receive port of the Phy Chip. It receives
the data serially. It performs address filtering thereby rejecting
the frames not destined to it. It rejects the duplicate or Invalid
frames. The invalidity of a frame may be due to CRC Error, Unsupported
protocol Version, Distributed system (DS) Error, Wired equivalent
privacy (WEP) error, Frame Type Error, Frame Sub Type Error,
Source Address Error. The Receiver updates TSF Timer and Network
Allocation Vector (NAV). |
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| Baseband Configuration
Block |
| Performs baseband chip configuration
depending upon the command signals coming from Receiver and
Command Decoder. Three Modes of configuration exist. Entire
Baseband chip configuration at Power On Reset, Baseband chip’s
transmitter configuration during every transmission, Baseband’s
transmit frame length registers and read Baseband’s Registers. |
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| Synthesizer Configuration
Block |
| Performs frequency synthesizer configuration
resulting in the station getting tuned to a particular channel.
The channel is programmable by the micro-controller. The configuration
comprises of Write operation into the Frequency Register of
synthesizer chip. The data transfer is serial. |
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MAC Access Point Architecture
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Illustrative Applications
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