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MindTree’s approach to WLAN Baseband design provides maximum
flexibility to chip vendors without compromising performance
parameters such as processor load and memory requirements.
Compliant with IEEE 802.11a specification, the WLAN Baseband
Core is available as silicon proven synthesizable Verilog
core. The core supports data rates of up to 54Mbit / s in
the 5GHz band and is based on OFDM technology.
Baseband architecture is flexible enough to support various
MAC and Radio implementations to enable optimal custom application
designs. With minimum chip power consumption, fabless companies
can customize Baseband to develop the lowest footprint SOC
design for any target application.
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| Features |
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Fully compliant
to IEEE 802.11a 5GHz Standard |
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Supports
all IEEE 802.11a data rates of 6, 9, 12, 18, 24, 36, 48, 54
Mbps |
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Implements
OFDM for better multipath tolerance |
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Supports
BPSK, QPSK, 16 QAM, 64 QAM Modulation schemes |
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Supports
FEC coding rates of 1/2, 2/2, 3/4 |
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Implements
64 Point Complex FFT/IFFT algorithm |
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Parallel
Interface to MAC for High Speed Data Transfer |
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Serial Interface
to MAC for PHY Configuration and Status Information |
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Implements
Automatic Gain Control |
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Easy Customization
to Different MAC and Radio Interfaces |
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| Deliverables |
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RTL synthesizable
Verilog core |
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Design and
verification documents |
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Synthesis
scripts |
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Test environment
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Golden test
cases |
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Application
documents |
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User manual
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| Typical Applications |
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Infrastructure
BSS Networks |
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Independent
BSS Networks |
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Multimedia
Applications |
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| Register
Bank |
| This block comprises
of the PHY Configuration and Status Registers. |
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| Transmission
Control |
| This block accepts MAC
Data and forwards to Transmitter. It controls the Transmit Data
Path. |
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| Reception
Control |
| This block forwards
received data to MAC. It controls the Receive Data Path. |
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| CCA |
| This block performs
clear channel assessment and provides Channel status to MAC. |
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| Scrambler
and De-scrambler |
| This block
uses the polynomial (x 7 + x 4 + 1) to scramble the data during
transmission and de-scramble the data during reception. |
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| Encoder
and Viterbi Decoder |
| The Convolution
encoder encodes Transmit Data with the coding rate of R = 1/2,
2/3 or 3/4. The Viterbi algorithm is used to decode data during
reception. |
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| Puncturing
and De-puncturing |
| Puncturing
enhances the encoding rate by omitting some encoded bits during
transmission. De-puncturing inserts the Dummy zero metric into
Viterbi Decoder in place of omitted bits. |
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| Modulator/Demodulator |
| This block implements
BPSK, QPSK, 16-QAM, 64-QAM modulation schemes. |
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| IFFT/FFT |
| This block implements
the 64-point complex FFT or IFFT algorithm. Inverse Fast Fourier
Transform of modulated symbols is used to obtain OFDM signal
during transmission, while FFT is applied during reception. |
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| Frequency
Synchronization |
| This block detects and
compensates the Carrier frequency offset |
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For further information, email:
wlan@mindtree.com |
