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MindTree’s approach to WLAN Baseband design provides maximum
flexibility to chip vendors without compromising performance
parameters such as processor load and memory requirements.
Compliant with IEEE 802.11b specification, the WLAN Baseband
Core is available as silicon proven synthesizable Verilog
core. The core supports data rates of up to 11Mbit/s in the
2.4GHz band and is based on DBPSK, DQPSK and CCK modulation
schemes.
Baseband architecture is flexible enough to support various
MAC and Radio implementations to enable optimal custom application
designs. With minimum chip power consumption, fabless companies
can customize Baseband to develop the lowest footprint SOC
design for any target application.
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| Features |
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Fully compliant
to IEEE 802.11b 2.4 GHz Std |
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Supports
all IEEE 802.11b data rates of 1, 2, 5.5, 11 Mbps |
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Supports
DBPSK, DQPSK, CCK Modulation schemes |
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Serial Interface
to MAC for PHY Configuration and Status Information |
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Implements
Automatic Gain Control For Transmit And Receive Path |
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Easy Customization
to Different MAC and Radio Interfaces |
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| Deliverables |
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Synthesizable
Verilog Source Code |
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Synthesis
scripts |
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Validation
Environment |
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Golden Test
cases |
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Design Documents |
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Application
Documents |
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User Manual
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| Typical Applications |
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Infrastructure
BSS Networks |
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Independent
BSS Networks |
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Multimedia
Applications |
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| Register
Bank |
| This comprises of Phy
configuration and status registers. The Phy configuration registers
are used to program the modulation technique, preamble type
for the packets to be transmitted and threshold values of the
RSSI. The status registers reflect the status of the received
packet. |
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| Transmission
Control |
| This accepts MAC Data
(MPDU - MAC Protocol Data Unit) and forwards them to the transmitter.
It controls the entire transmit data path including framing
of the PLCP PPDU (Physical Layer Convergence Protocol Data Unit),
scrambling and modulation of the PPDU. |
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| Reception
Control |
| This forwards received
data to the MAC. It controls the entire receive data path including
correlation, demodulation and descrambling. It also controls
the SFD, CRC - 16 check on the received packet and forwards
the received bit stream to the MAC. |
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| CCA |
| This performs clear
channel assessment based on the RSSI (Received Signal Strength
Indication) and correlation peaks. It also provides channel
status to the MAC. |
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| PLCP
Preamble/ SFD/ Header/ CRC - 16 Generation |
| This block
is used to frame the PLCP Preamble, SFD, PLCP Header, 16-bit
CRC on the signal, service and length field of the PLCP Header. |
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| PLCP
Preamble/ SFD/ Header/ CRC - 16 Detection |
| This block
is used to track the PLCP preamble, detect SFD, process the
PCLP Header and verify 16 Bit CRC on the signal, service and
length field of the PLCP header of the received frame. |
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| Scrambler
& Descrambler |
| This block
uses the polynomial G (z) = Z-7 + Z-4 + 1 for scrambling data
during transmission and descrambling data during reception. |
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| Modulator/Demodulator |
| It implements DBPSK,
DQPSK, CCK modulation and demodulation techniques for transmission
and reception respectively. |
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| Phase
Correction Logic |
| It detects and compensates
the carrier frequency offset. |
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| Radio
Control |
| It controls the DSSS
Radio Chip Set for data transmission and reception. It controls
the gain during transmit and receive paths for efficient data
transmission and reception through automatic gain Control logic. |
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For further information, email:
wlan@mindtree.com |
