Home Product Realization Intellectual Properties
© All products, services and company names are trademarks, registered marks or service marks of their respective companies.
 
Download PDF version > < Wireless LAN
 

MindTree’s approach to WLAN MAC design provides maximum flexibility to chip vendors without compromising performance parameters such as processor load and memory requirements. Compliant with IEEE 802.11 a/b and with IEEE 802.11e specifications, the WLAN MAC core with QoS functionality is available as silicon proven synthesizable Verilog core with protocol software. The IP can be reconfigured to work with any 8/16/32 bit microcontroller on which protocols reside and be reconfigured to interface with both a and b WLAN Baseband implementations.

Customers can quickly develop IEEE compliant 802.11 MAC chips with QoS or integrate the MAC with QoS functionality into SOC designs.

The MAC architecture is flexible enough to support various on-chip FIFOs and sizes to enable optimal custom application designs. With minimum processor load and and chip power consumption, fabless companies can easily customize MAC IP to develop the lowest foot print SOC design for both access point and station applications.

Framework comes here
Features
Supports
 
IEEE 802.11a/b station
IEEE 802.11e draft
Data rates up to 54 Mbps
Infrastructure/Independent BSS
Distributed Coordination Function (DCF)/Point Coordination Function (PCF)
Technology independent synthesizable verilog core
Configurable FIFO sizes
Generic host interface for microcontrollers
ACK/CTS Management
Base Band and frequency synthesizer configuration
Beacon frame monitoring and generation
WLAN traffic processing
Power management
Interface to Intersil's/RFMD's DSSS Radio chip set
Deliverables
RTL synthesizable core
Synthesis scripts
Test environment
Golden test cases
Design and verification documents
Application documents
User manual
Framework comes here
Host Interface
It interacts with Host allowing read and write data transactions From/To Host and Mac Controller internal blocks.
Command Decoder
It triggers Baseband controller and channel configuration (Frequency synthesizer configuration). It determines when the beacon interval occurs and accordingly gives an early TBTT (Target Beacon Transmission Time) indication.It possesses Local Timer, which is 64 bits, which is loaded with Time Stamp of Beacon/Probe Response frames. It has beacon timer, which ensures that every beacon interval there has to be beacon reception.
DCF/PCF

It implements DCF and PCF functionality. It implements virtual carrier sense mechanism leading to collision avoidance. It determines whether the medium is Idle or Busy for the transmission of Frames. It implements BackOff procedure.

It detects the start and end of the contention free period. It allows PCF transactions leading to Real Time Data Flow.
Interrupt Block
The Interrupt block raises Interrupt if any of the sources of Interrupt is active. It withdraws interrupt once all the sources of interrupt are cleared. Sources of interrupt can be masked through the interrupt mask register.
Register Bank
This comprises of the registers required for MAC operation. Host programs these registers whenever it wants to transmit a frame. There is a status register in read only mode, which indicates the status of MAC.
MAC FIFO Manager
This controls the FIFO Operation. There are two FIFOs used. One FIFO for the receive operation and the other FIFO for the transmit operation.
Transmitter
It deals with the transmission of MAC frames. It transmits only when it is triggered by DCF block. Prior to every transmission, Baseband configuration is performed. It interacts with the Transmit port of Phy Chip. It transmits data serially. It generates interrupts like ACK/CTS/TimeOut interrupts.
Receiver
It deals with the reception of MAC frames. It interacts with the receive port of Phy chip. It receives the data serially. It performs address filtering there by rejecting the frames not destined to it. It rejects the duplicate frames, and invalid frames. The invalidity of a frame may be due to CRC error, unsupported protocol version, Distribution system (DS) error, Wired Equivalent Privacy (WEP) Error, frame type error, frame subtype error, source address error. It updates TSF timer, and Network allocation Vector (NAV).
Baseband (BB) Config/Synth Config
It performs baseband, synthesizer configuration. Three modes of configuration exist.
Entire Baseband Configuration After Power On Reset
Baseband's Transmitter Configuration for every Frame Transmission
Baseband's Registers Read/Write whenever Host desires
It performs frequency synthesizer configuration resulting in the station getting tuned to a particular (Host programmed) channel. The configuration comprises of write operation into the frequency registers of synthesizer chip. The data transfer is serial.
Power Management
It performs power management procedure. It forces PowerDown Mode & PowerUp mode.
Channel Arbitor
It resolves arbitration amongst various queues using DCF procedure and allocates the transmission opportunity.
Queue Context Engine
It arbitrates for channel for each data queue. After getting opportunity, it triggers transmitter for baseband configuration and transmission of data. It enables DMA for data transfer from memory to Transmit FIFO.
Ack BitMap Generator
It generates Ack Bitmap for Burst QoS data traffic received.
CCI Block
It processes controlled contention frame received from HC, and transmits reservation request frame.
FEC Block
This block performs FEC on the transmit, received data based on Reed Solomon's code.